The data buffer (DB) is the dual 4-bit bidirectional data register with differential strobes is designed for 1.1 V operation. The DB device
has a dual 4-bit host bus interface that is connected to a memory controller and a dual 4-bit DRAM interface that is
connected to two x4 DRAMs. It also has an input-only control bus interface that is connected to a DDR5 RCD.
The DB device has the following capabilities for memory controller and memories. All data (DQ) inputs are pseudo-differential with an internal voltage reference. All DQ outputs are VDD terminated drivers
optimized to drive single or dual terminated traces in DDR5 and next-generation DDRx LRDIMM applications. The differential DQS strobes are
used to sample the DQ inputs and are regenerated in the DB for driving out the DQ outputs on the opposite
side of the device.
The clock inputs of the DB are used to sample the control inputs such as chip-select and DB communication signals which are used to write device internal control registers.
By using advanced analog/mixed-signal and digital SoC circuits, Deep-I can provide high-speed and energy-efficient DB memory buffer to enable high-performance computing systems.