Please submit your resume with your key work experiences via email (tech@deepi.co.kr) Qualified candidates will be contacted by the hiring team.
DRAM DFE/CTRL Layout: Memory (DDR4, DDR5) PHY layout High Speed TRX layout
Analog IO IC Design: Memory DDR4/5, CTLE/DEF, P/DLL mixed-signal IC design
Verilog/VHDL-based RTL design/ SoC-Protocol/Data-path RTL Verification
Frontend/back-end RTL synthesis/PnR Design Flow and SoC Verifiication
DDR DRAM memory controller FPGA / Verilog Digital/HW verification
HR support
R&D support
Administrative support
Basic Verilog/VHDL-based RTL design and SoC digital design verification
Memory Architect and DRAM (DDR and LR-DDR) and High-speed DRAM product