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Please submit your resume with your key work experiences via email (tech@deepi.co.kr) Qualified candidates will be contacted by the hiring team. 

DRAM PHY Layout Engineer

DRAM DFE/CTRL  Layout: Memory (DDR4, DDR5) PHY layout High Speed TRX layout

DRAM PHY Analog Engineer

Analog IO IC Design: Memory DDR4/5, CTLE/DEF, P/DLL mixed-signal IC design

DRAM RTL Design Engineer

Verilog/VHDL-based RTL design/ SoC-Protocol/Data-path  RTL Verification

Frontend/back-end Design Engineer

Frontend/back-end RTL synthesis/PnR Design Flow and SoC Verifiication

Memory Controller IP Design Engineer

DDR DRAM memory controller FPGA / Verilog Digital/HW verification

HR and administration 

HR support
R&D support
Administrative support

Entry-level RTL Design Engineer

Basic Verilog/VHDL-based RTL design and SoC digital design verification

Senior Principal Director

Memory Architect and DRAM (DDR and LR-DDR) and High-speed DRAM product